Verilog Parser Functions as Front End to Empyrean’s Library Quality Inspection Software Qualib
ALAMEDA, Calif., June 13, 2018 (GLOBE NEWSWIRE) — Verific Design Automation today announced Empyrean, provider of fast and physically aware, design closure and optimization solutions for systems on chip (SoCs), licensed its Parser Platform to function as the front end to Qualib, library quality inspection software.
“Verific is a company providing exceptional value,” says Lifeng Wu, Empyrean’s senior vice president. “Our development group is pleased with the quality and completeness of its product and comprehensive APIs. As a result, the integration between Qualib and Verific’s parser and elaborator was straightforward.”
Empyrean’s Qualib is a comprehensive platform to qualify libraries or intellectual property (IP) early in the design cycle when correcting errors is less costly than during final verification. With advanced features for analysis, debugging, cross-reference and reports generation, Qualib is used by design groups to inspect the consistency of third-party libraries and IP or library and IP creators for regular inspections. It supports multiple formats including Library Exchange Format (LEF), Graphic Database System (GDS), Timing Library Format (TLF), CADKey CADL Language (CDL) and Verilog netlists.
“Qualib is a great tool for implementing a ‘shift-left’ methodology,” remarks Michiel Ligthart, Verific’s president and chief operating officer. “Moving verification and library qualification earlier in the design flow is an ideal way to shave costs and reduce time to tape out. Verific is pleased to be part of this effort.”
Verific’s SystemVerilog, VHDL and universal power format (UPF) Parser Platforms are in production and development flows at semiconductor companies worldwide, from emerging companies to established Fortune 500 vendors. Applications range from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design for test. Verific distributes its Parser Platforms as C++ source code and compiles on all 32- and 64-bit Unix, Linux, Mac OS and Windows operating systems.
Founded in 2009, Empyrean is an Electronic Design Automation (EDA) and intellectual property (IP) technology leader delivering fast and true physically aware, design closure and optimization solutions for timing, clock and power of systems on chip (SoCs). The company offers a high-performance accurate circuit simulator and is an analog IP and fast Serdes IP provider. For details, go to: http://www.empyrean.com.cn/
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups to develop advanced electronic design automation (EDA) products quickly and cost effectively. Since 1999, Verific has shipped more than 60,000 copies of its software used worldwide by the EDA and semiconductor industry. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555.
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